- PhD, Stanford University, 2002
From 2002 to 2005, Dr. Tsai was a senior lithography process engineer of Intel Corporation. At Intel he worked on performance monitoring and improvement of 193-nm microlithography scanners at Fab-D1C in Hillsboro, Oregon, and Fab-11X in Rio Rancho, New Mexico, for Intel's P1262 90-nm process technology with 300-mm facilities. He also conducted research projects in the Advanced Mask Technology group of Components Research in Santa Clara, California, on defect inspection specifications and inspection tool development for EUV lithography targeted for 32-nm technology node and beyond.Dr. Tsai is a member of IEEE, SPIE, and the Phi Tau Phi Scholastic Hornor Society.